Kinds of optical sensor circuits which form pixels of a MOS image sensor are classified into three circuits. The first optical sensor circuit is an optical sensor circuit having a linear output characteristic with respect to a change in the illuminance (intensity) of incident light, the second optical sensor circuit is an optical sensor circuit having a logarithmic output characteristic with respect to a change in the illuminance of incident light, and the third optical sensor circuit is an optical sensor circuit having a linear output characteristic with respect to incident light with low illuminance, and a logarithmic output characteristic with respect to incident light with high illuminance. Hereinafter, these optical sensor circuits will be briefly described, and their characteristics will be evaluated in S/N ratio, dynamic range, residual image, sensitivity at low illuminance, etc.
FIG. 21 shows an example of an optical sensor circuit having a linear output characteristic. The optical sensor circuit 101 comprises a photodiode PD serving as an optical sensor device which detects incident light (light signal) L1 and converts it to an electric signal. The photodiode PD has a capacitor C1 which is a parasitic capacity (including stray capacitance of wirings). The optical sensor circuit 101 further comprises a MOS transistor Q1 which charges and discharges the capacitor C1, a MOS transistor Q2 for amplifying the terminal voltage of the capacitor C1, and a MOS transistor Q3 which selectively outputs the amplified terminal voltage (Vout) as a pixel signal. Hereinafter, the MOS transistor Q1 is referred to as “first MOS transistor Q1”, the MOS transistor Q2 is referred to as “second MOS transistor Q2”, and the MOS transistor Q3 is referred to as “third MOS transistor Q3”. A resistor R is connected to the drain terminal of the third MOS transistor Q3.
Required voltages V1, V2 are applied by a voltage controller 102 to the gate terminal G1 and drain terminal D1 of the first MOS transistor Q1. Similarly, required voltages V3, V4 are applied by the voltage controller 102 and the like (pixel selecting circuit and the like) to the gate terminal G3 of the third MOS transistor Q3 and an outer terminal T1 of the resistor R. The generation timings of the required voltages V1 to V4 output from the voltage controller 102 are instructed by a timing signal generating portion 103.
The operation of the optical sensor circuit 101 will be described. In a state where the drain voltage V2 of the first MOS transistor Q1 is maintained to a high level, the gate voltage V1 of the first MOS transistor Q1 is set to a high level at a timing of initialization. This eliminates charges remaining in the capacitor C1 of the photodiode PD to the drain of the first MOS transistor Q1. Then, the gate voltage V1 is switched to a low level (0 V) to turn off the first MOS transistor Q1. Thereafter, the capacitor C1 of the photodiode PD is caused to accumulate charges. The terminal voltage of the capacitor C1 which is produced by the accumulation of charges is applied to the gate of the second MOS transistor Q2. When, after elapse of a constant exposure time in the photodiode PD, the light signal is output as the voltage Vout from the drain of the third MOS transistor Q3.
In the optical sensor circuit 101, the photocurrent flowing through the photodiode PD is dominated by a discharge current of charges charged in the capacitor C1 of the photodiode PD. Therefore, the output voltage Vout which is a sensor output of the optical sensor circuit 101 shows the linear output characteristic which is proportional to the discharge current. The optical sensor circuit 101 can control the sensor output on the basis of the exposure time, and hence becomes a storage type image sensor. In the circuit configuration of the optical sensor circuit 101, however, the output voltage Vout is proportional to the intensity of the incident light L1, and, when strong light is incident, the circuit saturates. Therefore, the circuit has a problem in that the dynamic range cannot be largely widened.
An optical sensor circuit having a circuit configuration which is similar to the optical sensor circuit 101 is shown in FIG. 7 and the like of Patent Reference 1.
Next, FIG. 22 shows an example of an optical sensor circuit having a logarithmic output characteristic. In FIG. 22, components which are substantially identical with those illustrated with reference to FIG. 21 are denoted by the same reference numerals, and duplicated detailed description of the components is omitted. In the optical sensor circuit 201, a MOS transistor Q21 is used in place of the first MOS transistor Q1 of the optical sensor circuit 101. In the MOS transistor Q21, the gate is electrically connected to the drain. The MOS transistor Q21 corresponds to the first MOS transistor Q1 to be used in place of it, and hence is referred to as “first MOS transistor Q21”. The photodiode PD, the capacitor C1, the second MOS transistor Q2, the third MOS transistor Q3, the resistor R, and the other circuit configuration are identical with those illustrated with reference to FIG. 21. In the optical sensor circuit 201, the first MOS transistor Q21 converts the sensor current of the photodiode PD to a sensor voltage having a logarithmic characteristic in a weak inversion state.
In the optical sensor circuit 201, the gate of the first MOS transistor Q21 is connected to the drain of the transistor, the drain and gate voltages are set to the same constant drain voltage V2, and the third MOS transistor Q3 is turned on to output the light signal as the output voltage Vout. A high-level gate voltage from the voltage controller 102 is supplied to the gate terminal G3 of the third MOS transistor Q3.
In the optical sensor circuit 201, the dynamic range can be widened in order to use the logarithmic output characteristic. However, the photocurrent flows via the channel of the first MOS transistor Q21, and hence the S/N ratio cannot be improved by lengthening the exposure time unlike a storage type image sensor. Therefore, the sensitivity for low illuminance is lower than that of a storage type image sensor based on the optical sensor circuit 101. When the current flowing through the first MOS transistor Q21 is small, the impedance of the channel is high, and hence there arises a problem in that a residual image easily occurs.
An optical sensor circuit having a logarithmic output characteristic is disclosed in Patent Reference 1.
FIG. 23 shows an example of an optical sensor circuit having a linear output characteristic with respect to the incident light L1 with low illuminance, and a logarithmic output characteristic with respect to incident light with high illuminance. The circuit configuration of the optical sensor circuit 301 shown in FIG. 23 is identical with that of the optical sensor circuit 101, components which are identical with those illustrated in FIG. 21 are denoted by the same reference numerals, and their description is omitted. The gate voltage Vg is supplied to the gate of the first MOS transistor Q1, and the drain voltage Vd is supplied to the drain of the transistor. FIG. 24 shows voltage waveforms of the supplied gate and drain voltage Vg and Vd. In the optical sensor circuit 301, the drain voltage Vd of the first MOS transistor Q1 is set to a predetermined value (Vd1), and the gate voltage Vg is set to a voltage (Vg1: high level (H)) which is sufficiently higher than the drain voltage Vd, only for a predetermined time period (t2−t1), whereby the circuit is controlled so as to charge and discharge the capacitor C1 of the photodiode PD connected to the source. The control is executed by the voltage controller 102 and the timing signal generating portion 103. The functional portion which executes the control is called “initial setting means”. The other configuration is identical with the optical sensor circuit 101 illustrated with reference to FIG. 21.
The operation of the optical sensor circuit 301 will be described with reference to the timing chart (voltage waveform chart) shown in FIG. 24. The drain voltage Vd is set to the constant voltage value (Vd1) by which, when the gate voltage Vg is at a low level (L), a current flowing through the first MOS transistor Q1 is converted to a voltage having a logarithmic output characteristic in a weak inversion state.
In the above-described state, the gate voltage Vg is set to a high voltage (Vg1: high level) during t1 to t2. As a result, the first MOS transistor Q1 is set to the on state, the channel impedance of the first MOS transistor Q1 is a low resistance, and the voltage of the source terminal, i.e., the terminal voltage VC1 of the capacitor C1 is charged to a value which is similar to the drain voltage Vd. Hereinafter, this operation is referred to as “reset operation”.
Nest, at the timing of t2, the gate voltage Vg is switched to the low level. During t2 to t3, the photocurrent flowing through the photodiode PD is dominated by a discharge current of charges charged in the capacitor C1 of the photodiode PD. Therefore, the terminal voltage VC1 of the capacitor C1 is lowered during a time interval of t2 to t3 by the discharging of charges, and the sensor output shows a linear output which is proportional to the discharge current. During the time interval of t2 to t3, the output is a linear output region 302. When the terminal voltage VC1 of the capacitor C1 is further lowered by discharging of charges, after the timing of t3, the photocurrent flowing through the photodiode PD is dominated by the current supplied from the first MOS transistor Q1, and the sensor output is converted to a voltage having a logarithmic characteristic, and shows a logarithmic output. During the time interval of t3 to t4, the output is a logarithmic output region 303.
The optical sensor circuit 301 comprises: the linear output region 302 where, in the case where the photocurrent of the photodiode PD is weak, a voltage which is proportional to the discharge current of the capacitor C1 is detected; and the logarithmic output region 303 where, in the case where the photocurrent of the photodiode PD is large, a voltage having a logarithmic characteristic is detected. Therefore, the optical sensor circuit 301 can accurately detect weak light, and widen the dynamic range.
Furthermore, the optical sensor circuit 301 can average noises by means of an integral operation of the capacitor C1, and therefore the S/N ratio can be improved so that the lower limit of the detectable range of the light illuminance is further lowered, thereby enabling a high sensitivity to be realized. Accordingly, it is possible to realize an optical sensor circuit in which the S/N ratio is high, the sensitivity is high, and the dynamic range is wide.
However, the optical sensor circuit 301 has a problem in that, in the case where the circuit is configured as one pixel and such pixels are connected in a two-dimensional matrix pattern to form an imaging region and constitute a two-dimensional image sensor, a point of change between the region having a linear output characteristic and that having a logarithmic output characteristic is dispersed among pixels.
FIG. 25 is a characteristic diagram showing dispersion of the incident light intensity (abscissa) and the sensor output (ordinate) among pixels of a two-dimensional image sensor. In the figure, for example, a difference between the sensor output voltage at each incident light intensity and the output voltage in a dark state is plotted with respect to six pixels. The dispersion of the sensor output is caused by that of the threshold of the first MOS transistor Q1.
The cause of the dispersion will be described with reference to FIG. 26. In FIG. 26, two pixels A, B produced by the optical sensor circuit 301 are shown in the abscissa direction, and the potential state of the terminal voltage VC1 of the capacitor (parasitic capacity) C1 is shown in the direction of the ordinate. In the ordinate showing the terminal voltage VC1, the upper side corresponds to “dark”, and the lower side to “bright”. Immediately after the above-mentioned reset operation, the terminal voltage VC1 of the capacitor C1 of the photodiode PD is a potential equivalent to the drain voltage Vd in both the pixels A, B (state 310). Thereafter, the photocurrent flowing through the photodiode PD is dominated by a discharge current of charges charged in the capacitor C1 of the photodiode PD. Hence, the terminal voltage VC1 is lowered by discharging, and the sensor output shows a linear output characteristic (302A, 302B) which is proportional to the discharge current. When the terminal voltage VC1 is further lowered by discharging of charges, the current supplied from the first MOS transistor Q1 is dominant so that the sensor output shows a logarithmic output characteristic (303A, 303B).
The points of change between the regions (302A, 302B) showing a linear output and the regions (303A, 303B) showing a logarithmic output relate to the threshold (Vth) of the first MOS transistor Q1. When the threshold is dispersed as VthA, VthB, therefore, the potential of the point of change is different depending on pixels. In all the pixels, however, the terminal potentials immediately after the reset are the drain voltage Vd and common (state 310). Accordingly, the potential difference between the terminal potential immediately after the reset and the above-mentioned point of change (304A, 304B) is different between the pixels A, B. In this way, due to the phenomenon that the potential difference between the terminal potential immediately after the reset and the above-mentioned point of change is different between the pixels A, B, the region having a linear characteristic is dispersed among pixels.
Patent Reference 2 discloses an optical sensor signal processing apparatus which solves the problem in the optical sensor circuit 301. In the optical sensor signal processing apparatus, a fixed pattern noise due to dispersion of characteristics of pixels in a MOS image sensor is suppressed, and dispersion of output characteristics at an inflection point where the output of each pixel is switched from the linear characteristic region to the logarithmic characteristic region is corrected. Therefore, a table for correcting the output value is disposed for each pixel (optical sensor circuit), so that the output value of each pixel is corrected.
Patent Reference 1: JP-A-2000-329616
Patent Reference 2: JP-A-11-298799